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1 of 18 021800 features integrated nv sram, real time clock, crystal, power-fail control circuit and lithium energy source clock registers are accessed identical to the static ram. these registers are resident in the eight top ram locations. century byte register; ie., y2k compliant totally nonvolatile with over 10 years of operation in the absence of power bcd coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 battery voltage level indicator flag power-fail write protection allows for 10% v cc power supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time dip module only - standard jedec byte-wide 32k x 8 static ram pinout powercap module board only - surface mountable package for direct connection to powercap containing battery and crystal - replaceable battery (powercap) - power-on reset output - pin for pin compatible with other densities of ds174xp timekeeping ram pin assignment ds1744/ds1744p y2kc nonvolatile timekeeping ram www.dalsemi.com 1 nc 2 3 nc nc rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 nc x1 gnd v bat x2 34-pin powercap module board (uses ds9034pcx powercap) vcc we a 13 a 8 a 9 a 11 oe a 10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin encapsulated package (700 mil extended)
ds1744/ds1744p 2 of 18 pin description a0?a14 ? address input ce ? chip enable oe ? output enable we ? write enable v cc ? power supply input gnd ? ground dq0?dq7 ? data input/output nc ? no connection rst ? power?on reset output(power? cap module board only) x1, x2 ? crystal connection v bat ? battery connection ordering information ds1744p?xxx (5 volt) -70 70 ns access -100 100 ns access blank 28-pin dip module p 34-pin powercap module board* ds1744wp-xxx (3.3 volt) -120 120 ns access -150 150 ns access blank 28-pin dip module p 34-pin powercap module board* *ds9034pcx (powercap) required: (must be ordered separately) description the ds1744 is a full function, year 2000 compliant (y2kc), real?time clock/calendar (rtc) and 32k x 8 non?volatile static ram. user access to all registers within the ds1744 is accomplished with a bytewide interface as shown in figure 1. the real time clock (rtc) information and control bits reside in the eight uppermost ram locations. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 hour bcd format. corrections for the date of each month and leap year are made automatically. the rtc clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. the double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. the ds1744 also contains its own power?fail circuitry which deselects the device when the v cc supply is in an out of tolerance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided.
ds1744/ds1744p 3 of 18 ds1746 block diagram figure 1 packages the ds1744 is available in two packages (28?pin dip and 34?pin powercap module). the 28?pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34?pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the power-cap to be mounted on top of the ds1744p after the completion of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part number for the powercap is ds9034pcx. clock operations-reading the clock while the double buffered register structure reduces the chance of reading incorrect data, internal updates to the ds1744 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a one is written into the read bit, bit 6 of the century register, see table 2. as long as a one remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the ds1744 registers are updated simultaneously after the internal clock register updating process has been reenabled. updating is within a second after the read bit is written to zero.
ds1744/ds1744p 4 of 18 ds1744truth table table 1 v cc ce oe we mode dq power v ih x x deselect high-z standby v il xv il write data in active v il v il v ih read data out active v cc >v pf v il v ih v ih read high-z active v so ds1744/ds1744p 5 of 18 ds1744 register map table 2 data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 7ffff 10 year year year 00-99 7fffe x x x 10 mo month month 01-12 7fffd x x 10 date date date 01-31 7fffc bf ft x x x day day 01-07 7fffb x x 10 hour hour hour 00-23 7fffa x 10 minutes minutes minutes 00-59 7fff9 osc 10 seconds seconds seconds 00-59 7fff8 w r 10 century century century 00-39 osc = stop bit r = read bit ft = frequency test w = write bit x = see note below bf = battery flag note: all indicated ?x? bits are not dedicated to any particular function and can be used as normal ram bits. retrieving data from ram or clock the ds1744 is in the read mode whenever oe (output enable) is low, we (write enable) is high, and ce (chip enable) is low. the device architecture allows ripple-through access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times and states are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe. if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the ds1744 is in the write mode whenever we, and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce. the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active.
ds1744/ds1744p 6 of 18 data retention mode the 5 volt device is fully accessible and data can be written or read only when v cc is greater than v pf . however, when v cc is below the power fail point, v pf , (point at which write protection occurs) the internal clock registers and sram are blocked from any access. at this time the power fail reset output signal (rst) is driven active and will remain active until v cc returns to nominal levels. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3 volt device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power fail point, v pf , access to the device is inhibited. at this time the power fail reset output signal (rst) is driven active and will remain active until v cc returns to nominal levels. if v pf is less than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the rst signal is an open drain output and requires a pull up. except for the rst, all control, data, and address signals must be powered down when v cc is powered down. battery longevity the ds1744 has a lithium power source that is designed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1744 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at 25 c with the internal clock oscillator running in the absence of v cc power. each ds1744 is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1744 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. battery monitor the ds1744 constantly monitors the battery voltage of the internal battery. the battery flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. this bit is not writable and should always be a one when read. if a zero is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable.
ds1744/ds1744p 7 of 18 absolute maximum ratings* voltage on any pin relative to ground ?0.3v to +6.0v operating temperature 0 c to 70 c storage temperature ?20 c to +70 c soldering temperature 260 c for 10 seconds (see note 7) * this is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes v ih 2.2 v cc +0.3v v 1 logic 1 voltage all inputs v cc = 5v 10% v cc = 3.3v 10% v ih 2.0 v cc +0.3v v 1 v il -0.3 0.8 v 1 logic 0 voltage all inputs v cc = 5v 10% v cc = 3.3v 10% v il -0.3 0.6 v 1 dc electrical characteristics (0 c to 70 c; v cc = 5.0v = 10%) parameter symbol min typ max units notes active supply current icc x 75 ma 2,3 ttl standby current (ce = v ih ) icc 1 x 6 ma 2,3 cmos standby current (ce v cc -0.2v) icc 2 x 4 ma 2,3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1 ma) v ol 0.4 1 write protection voltage v pf 4.25 4.37 4.50 v 1 battery switch over voltage v so v bat 1,4
ds1744/ds1744p 8 of 18 dc electrical characteristics (0c to 70c; v cc = 3.3v 10%) parameter symbol min typ max units notes active supply current icc x 30 ma 2,3 ttl standby current (ce = v ih ) icc 1 x 2 ma 2,3 cmos standby current (ce v cc -0.2v) icc 2 x 2 ma 2,3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1 ma) v ol 0.4 1 write protection voltage v pf 4.25 4.37 2.97 v 1 battery switch over voltage v so v bat or v pf v 1,4 read cycle, ac characteristics (0c to 70c; v cc = 5.0v 10%) 70 ns access 100 ns access parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq low-z t cel 55ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq low-z t oel 55ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 55ns
ds1744/ds1744p 9 of 18 read cycle, ac characteristics (0c to 70c; v cc = 3.3v 10%) 120 ns access 150 ns access parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq low-z t cel 55ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq low-z t oel 55ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 55ns read cycle timing diagram
ds1744/ds1744p 10 of 18 write cycle, ac characteristics (0c to 70c; v cc = 5.0v 10%) 70 ns access 100 ns access parameter symbol min max min max units notes write cycle time t wc 70 100 ns address setup time t as 00 ns we pulse width t wew 50 70 ns ce pulse width t cew 60 75 ns data setup time t ds 30 40 ns data hold time t dh1 0 0 ns 8 data hold time t dh2 x x ns 9 address hold time t ah1 5 5 ns 8 address hold time t ah2 x x ns 9 we data off time t wez 25 35 ns write recovery time t wr 55 ns write cycle, ac characteristics (0c to 70c; v cc = 3.3v 10%) 120 ns access 150 ns access parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 00 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns ce and ce2 pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh1 0 0 ns 8 data hold time t dh2 x x ns 9 address hold time t ah1 0 0 ns 8 address hold time t ah2 x x ns 9 we data off time t wez 40 50 ns write recovery time t wr 10 10 ns
ds1744/ds1744p 11 of 18 write cycle timing diagram, write enable controlled write cycle timing diagram, chip enable controlled
ds1744/ds1744p 12 of 18 power?up/down ac characteristics (0 c to 70 c; v cc = 5.0v = 10%) parameter symbol min typ max units notes ce or we at v h before power-down t pd 0 s v cc fall time: v pf (max) to v pf (min) t f 300 s v cc fall time: v pf (min) to v so t fb 10 s v cc rise time: v pf (min) to v pf (max) t r 0 s power-up recover time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5,6 power?up/power?down timing 5 volt device
ds1744/ds1744p 13 of 18 power?up/down characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol min typ max units notes ce or we at v h , before power-down t pd 0 s v cc fall time: v pf (max) to v pf (min) t f 300 s v cc rise time: v pf (min) to v pf (max) t r 0 s v pf to rst high t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5,6 power?up/down waveform timing 3.3 volt device capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7pf capacitance on all output pins c o 10 pf
ds1744/ds1744p 14 of 18 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0.0 to 3.0 volts timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1. voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. battery switch over occurs at the lower of either the battery terminal voltage or v pf . 5. data retention time is at 25 c. 6. each ds1744 has a built?in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules and assembled powercap modules as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 7. real?time clock modules (dip) can be successfully processed through conventional wave? soldering tecniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultra-sonic vibration is not used. in addition, for the powercap: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live ? bug?). b. hand soldering and touch?up: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 8. t ah1 , t dh1 are measured from we going high. 9. t ah2 , t dh2 are measured from ce going high.
ds1744/ds1744p 15 of 18 ds1744 28?pin package pkg 28-pin dim min max a in. mm 1.470 37.34 1.490 37.85 b in. mm 0.675 17.75 0.740 18.80 c in. mm 0.335 8.51 0.355 9.02 d in. mm 0.075 1.91 0.105 2.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.45 k in. mm 0.015 0.43 0.025 0.58
ds1744/ds1744p 16 of 18 ds1746p pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live ? bug?). hand soldering and touch?up: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
ds1744/ds1744p 17 of 18 ds1744p with ds9034pcx attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 components and placement may vary from each device
ds1744/ds1744p 18 of 18 recommended powercap module land pattern inches pkg dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 -

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